1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly relate to a semiconductor device including a level shift circuit that converts the voltage amplitude of a signal.
2. Description of Related Art
Some semiconductor devices include a level shift circuit that converts the amplitude of a signal. There are two types of the level shift circuit, one of which is designed to decrease the signal amplitude and the other is designed to increase the signal amplitude. Among the two types, the level shift circuit designed to decrease the signal amplitude can foe configured by a simple inverter circuit. This is because the amplitude of the input-signal is larger than the amplitude of the operating voltage of the inverter circuit, and therefore at either logic level of the input signal, one of the transistors that constitute the inverter circuit can be reliably switched to the off state.
On the other hand, when the level shift circuit designed to increase the signal amplitude is configured by a simple inverter circuit, one of the transistors that constitute the inverter circuit cannot foe reliably switched to the off state depending on the logic level of the input signal. This causes a leak current. Therefore, in the level shift circuit designed to increase the signal amplitude, a circuit method as described in Japanese Patent Application Laid-open No. 2001-36388, in which two cross-coupled transistors are used, and an input signal and its inverted signal are used to turn on either one of the transistors, is mainly employed.
However, in the level shift circuit described in Japanese Patent Application Laid-open No. 2001-36388, there is sometimes a difference between the timing at which an output signal is changed in response to a change of an input signal from a first logic level to a second logic level and the timing at which an output signal is changed in response to a change of an input signal from the second logic level to the first logic level. When there is the difference between the timings as described above, it causes a difference in duty ratio between the input signal and the output signal. Therefore, a problem arises, for example, in that the effective width (window width) of read data is decreased,